1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor integrated circuit device, and more particularly to a fabrication method that permits the self-aligned formation of a contact window in a semiconductor integrated circuit device.
2. Description of the Prior Art
A method of the self-aligned formation of a contact window is known for forming a fine-featured contact window reaching down a semiconductor substrate through an insulating film covering transistor devices integrated in high density on the semiconductor substrate. According to this method, in order to form a contact on a small area of a substrate flanked by electrodes of transistor devices, an insulating film is etched using a mask having an opening larger than that small area to form a contact window in self-aligning fashion with respect to the electrodes. The contact made between the semiconductor substrate and the conductive layer (conductive line) via the thus formed contact window is referred to as a "self-aligned contact".
Referring to FIGS. 9A to 9D, we will describe a prior art method for forming a contact window in self-aligning fashion with respect to gate electrodes in a dynamic random access memory (DRAM). This prior art method is known as the FOBIC method and is disclosed, for example, in Symposium VLSI Technical Digest 93 (1987).
As shown in FIG. 9A, MOSFETs are formed in a device region of a semiconductor substrate 2. Each MOSFET consists of source/drain regions 6 formed in the semiconductor substrate 2, a gate insulating film 1 on the semiconductor substrate 2, and a gate electrode 4 formed above the channel region between the source/drain regions 6. The gate electrode 4 is covered with side wall spacers 5 and an upper insulating film 8. The side wall spacers 5 and the upper insulating film 8 are formed from a silicon dioxide film. The source/drain region 6 formed in an area flanked by two gate electrodes 4 is shared by the two adjacent MOSFETs. A thin first silicon oxide film 42, a silicon nitride film 43, and a second silicon oxide film 44 are successively deposited one on top of the other on the semiconductor substrate 2 in such a way as to cover the MOSFETs, after which a resist 3 having an opening that defines the position of a contact window is formed on top of the second silicon oxide film 44 by photolithography.
Next, as shown in FIG. 9B, using the resist 3 as an etching mask, isotropic wet etching is performed to etch the portion of the second silicon oxide film 44 exposed through the opening in the resist 3, to expose the surface of the silicon nitride film 43 therebelow. Since the etchant (hydrofluoric etchant) used for etching the silicon oxide film 44 does not virtually etch silicon nitride film 43, the silicon nitride film 43 acts as an etch stop layer. Thereafter, anisotropic dry etching is performed to etch the silicon nitride film 43 and the first silicon oxide film 42, to form a contact window 50 as shown in FIG. 9C. After removing the resist 3, a bit line 12 consisting of a polycrystalline silicon film 12a and a titanium silicide film 12b is formed as shown in FIG. 9D.
According to the above prior art, since wet etching is used to etch the second silicon oxide film 44, the second silicon oxide film 44 is etched deeply in lateral directions, enlarging the inner diameter of the contact window 50. Therefore, this method is not suitable for forming a fine-featured contact window with a large aspect ratio. Also, appreciable irregularities (steps) are formed on the surface of the second silicon oxide film 44 because of the presence of the gate electrodes 4 therebeneath, the size of the steps being proportionate to the thickness of the gate electrodes 4 and the upper insulating film 8. When the bit line 12 is formed by patterning the polycrystalline silicon film 12a and the titanium silicide film 12b after depositing these conductive films 12a and 12b on the second silicon oxide film 44, failures such as breaks or shorts of the bit line 12 are likely to occur because of the irregularities on the surface of the underlying layer (second silicon oxide film 44). FIG. 10A is a plan view showing the geometry of the bit line 12. FIG. 10B is a cross section taken along line B--B in FIG. 10A. As shown in FIG. 10B, the polycrystalline silicon film 12a deposited into a narrow recessed portion formed between the two gate electrodes 4 is not easy to remove, even by selective etching for forming the bit line 12, and is likely to remain in the narrow recessed portion. The residues of the conductive substance causes the bit line 12 to short to other bit lines as shown in FIG. 10A. If the etching is performed for an extended duration of time until the polycrystalline silicon film 12a is completely removed from the recessed portion, the width of the bit line 12 will become thinner than the design value, resulting in an increased resistance or breakage of the line.
Referring to FIGS. 11A to 11D, we will describe another prior art method proposed to overcome the above problem. This prior art is disclosed in the 22nd conference on Solid State Devices and Materials.
First, after forming MOSFETs in a device region of a semiconductor substrate 2 in a similar manner to the foregoing prior art, a silicon nitride film 43, a polycrystalline silicon film 41, and a BPSG (Borophosphosilicate glass) film 11 are successively formed one on top of the other on the semiconductor substrate 2, to cover the MOSFETs. Next, a resist 3 having an opening that defines the pattern of a contact window is formed on top of the BPSG film 11 by photolithography. BPSG is a silicon oxide containing impurities (boron, phosphorus) in large quantities (on the order of a few mol %), and has properties that softens and flows when heat-treated at about 900.degree. C. Therefore, the irregularities formed on the surface of the BPSG film 11 immediately after the deposition can be moderated by performing a heat treatment process (flow process), flattening the surface of the BPSG film 11 to a certain extent.
As shown in FIG. 11B, using the resist 3 as an etching mask, anisotropic dry etching is performed to etch the portion of the BPSG film 11 exposed through the opening in the resist 3, to expose the surface of the polycrystalline silicon film 41, an underlying layer. According to a conventional anisotropic dry etching technique, the polycrystalline silicon film 41 is resistive to etching under the conditions for etching BPSG and therefore acts as an etch stop layer. Thereafter, the polycrystalline silicon film 41 is etched by anisotropic dry etching under the conditions for etching polycrystalline silicon, to expose the surface of the silicon nitride film 43.
After removing the resist 3, pyro oxidation is performed to completely oxidize the polycrystalline silicon film 41 and transform it into a silicon dioxide film 46. At the same time, a flow process is performed to flatten the surface of the BPSG film 11. During the pyro oxidation, the silicon nitride film 43 serves to prevent the oxidation of the source/drain regions 6. After etching away the silicon nitride film 43 to open a contact window 7, a bit line 12 consisting of a polycrystalline silicon film 12a and a titanium silicide film 12b is formed.
According to the above prior art, since anisotropic dry etching is used to etch the BPSG film 11, a contact window 7 with a high aspect ratio can be formed. However, since a conductive film, i.e. the polycrystalline silicon film 41, is used as an etch stop layer during the etching of the BPSG film 11, there arises the necessity thereafter to completely oxidize the polycrystalline silicon film 41 and transform it into an insulating film (silicon dioxide film 46). If the insulation is insufficient, conductive portions having insufficient insulation will remain in the silicon dioxide film 46, and there is a possibility that the bit line 12 may short to other bit lines (not shown in FIG. 1H) via the conductive residues.
The pyro oxidation process for oxidizing the polycrystalline silicon film 41 is performed at high temperatures of approximately 900.degree. C. Therefore, if performed for an extended duration of time, this process may lead to the oxidation of the surfaces of the source/drain regions 6 or diffusion of impurities in the semiconductor substrate, thereby changing the transistor properties. It is therefore desirable that the polycrystalline silicon film 41 be completely oxidized by the oxidation process of short duration, which requires the thickness of the polycrystalline silicon film 41 to be approximately 30 nm at the maximum.
On the other hand, if the polycrystalline silicon film 41 is thin, the polycrystalline silicon film 41 may not be able to adequately serve as an etch stop layer during the etching of the BPSG film 11, the result being that the silicon nitride film 43 below the polycrystalline silicon film 41 may be etched and, in some cases, the gate electrode 4 may be exposed. The polycrystalline silicon film 41 of the thickness thinner than approximately 50 nm will not adequately serve as an etch stop layer.
Referring to FIGS. 12A to 12C, we will described in detail some of the problems that may arise when the thickness of the polycrystalline silicon film 41 is reduced. When etching the BPSG film 11, it is necessary to shorten the etching time of the BPSG film 11 so that the thin polycrystalline silicon film 41 will not be etched. As a result, a residual portion 11a of the BPSG film 11 is left at the side of side wall spacers 5. Since the residual portion 11a acts as an etching mask during the etching of the polycrystalline silicon film 41, a residual portion 41a of the polycrystalline silicon film 41 is left below the residual portion 11a, as shown in FIG. 12A. The residual portion 41a is not completely oxidized, leaving the polycrystalline silicon film 41 partially unoxidized (this unoxidized portion is indicated by 41b in FIG. 12B). Also, partially unoxidized portions 41C are formed along both sides of the gate electrodes 4 where the contact window 7 is not formed. Accordingly, when the bit line 12 is formed thereafter, the bit line 12 shown in FIG. 12C is shorted via the residual portion 41b to another bit line (not shown in FIG. 12C) formed in parallel to that bit line 12.
If the etching of the BPSG film 11 is performed for a long duration of time, despite the thinness of the polycrystalline silicon film, to avoid the above problem, not only the polycrystalline silicon 41 but also the upper insulating film 8 therebelow and a portion of the side wall spacer 5 will be etched, as shown in FIG. 13A. This etching will also cause the surfaces of the source/drain regions 6 to be exposed. As a result, as shown in FIG. 13B, the surfaces of the source/drain regions 6 are oxidized to form an oxide layer 47 during the oxidation process for the polycrystalline silicon film 41, requiring etching to remove the oxide layer 47 on the source/drain regions 6 before forming the bit line 12. However, this etching is very likely to cause the exposure of the gate electrodes 4. An exposed gate electrode 4 would be shorted to the bit line 12, as shown in FIG. 13C.